At present, Type-C, as an emerging universal serial bus (USB) interface standard, can provide a high data transmission speed, a high-power online power supply capability and a simple system connection under the support of the USB-PD protocol. In addition, Type-C can support simultaneous transmission of USB3.1 data and various video data including DisplayPort (DP), High Definition Multimedia Interface (HDMI) and Mobile High-Definition Link (MHL) and the like. According to the USB-PD specification, an upstream device communicates with a downstream device in the Type-C based on a Biphase Mark Coding (BMC) encoding mechanism through a configuration channel (CC). Rising edges or falling edges of a BMC-encoded transmission waveform are strictly specified in the USB-PD protocol. However, due to the uncertainty of parasitic parameters of a Type-C connection system, it is required that the rising or falling edges of the transmission waveform are adjustable, to ensure that the transmission waveform does not depend on the system connection property and conforms to the USB-PD specification.
A conventional BMC transceiver includes two independent parts, that is, a BMC transmitter and a BMC receiver. As shown in FIG. 1, a schematic diagram of a conventional BMC transceiver is shown. A BMC transmitter of the BMC transceiver includes a push-pull driving output circuit 01 and a rising/falling edge control circuit 02. A BMC receiver of the BMC transceiver includes a comparator 03 and a reference voltage generating circuit 04. The push-pull driving output circuit 01 and the rising/falling edge control circuit 02 constitute a digital circuit, and the comparator 03 and the reference voltage generating circuit 04 constitute an analog circuit. Since the two circuits have different natures, and a power supply of the push-pull driving output circuit 01 and the rising/falling edge control circuit 02 has a large switching noise which may affect a comparison result of the comparator 03 and the reference voltage generating circuit 04, it is required to properly isolate the two circuits in a layout. In addition, in the conventional BMC transmitter, an architecture as shown in an example in FIG. 2 is adopted. FIG. 2 shows a conventional BMC transmitter with a controlled slew rate. Input data di is sampled by n stages of clocks to obtain signals d0 to dn with equal intervals (the interval refers to a clock period Tck). Then, the signals d0 to dn are transmitted to the same number of buffers BUF, such that the n BUFs are successively driven to output a waveform with controlled rising/falling edges, as shown in an upper part of FIG. 3. The slew rate may be changed by changing the clock frequency, that is, the clock period Tck. Waveforms under a light load and a heavy load are shown in a lower part of FIG. 3, it can be seen from the waveforms that there are obvious rising/falling edge steps, which are filtered out by a filter in an actual operation of the circuit; and a waveform with smooth rising/falling edges is finally obtained, as shown in the upper part of FIG. 3. However, the conventional BMC transceiver has the following disadvantages. First, the BMC transmitter is a digital circuit in nature, and the BMC receiver is an analog circuit in nature, it is required to isolate two circuits in a power supply and a ground to a certain degree, to prevent an interaction between power supply systems of the digital module and the analog module. Secondly, in the architecture adopted by the conventional BMC transmitter (as shown in FIG. 2), although the rising/falling edges are adjusted by means of multiple clocks with an equal interval phase or data sampled by multiple stages, these equal interval data or the clock drives digital buffers, which not only results in a large power supply switching noise, but also occupies a large chip area and consumes a large power.